Tutorial-1
Tutorial Title: Challenges of Digital Design Verification
Abstract: It is estimated that 50% to 70% of the engineering resources in a chip design company are spent on design verification. Writing testbenches, Simulation and debugging, Writing and running assertions, estimating and improving functional coverage, running regression tests and debugging constitute the activities of design verification engineers. System Verilog, along with Universal Verification Methodology, has gained traction in the industry for verification of large and complex digital designs. The purpose of this hands-on tutorial is to expose the participants to the above concepts in design verification. The tutorial will also bring out why artificial intelligence and machine learning are being explored in tasks such as achieving functional coverage closure. It is assumed that participants have taken a course in digital design and have a working knowledge of Verilog or VHDL. Candidates must bring their own laptop and must have access to Internet.
Brief profile of organizer:
C.P. Ravikumar is the Chief Learning Officer at Vinyana Tech, Bangalore. He is an Adjunct Professor
at IIT Madras and IIIT, Dharwad. Earlier, he has served as the Director of Technical Talent
Development at TI (India), as Vice President (Training) at Control Net India and as Professor of
Electrical Engineering at IIT Delhi.
Ravikumar obtained a Ph.D. in Computer Engineering from the Department of EE-Systems at University of Southern California (1991). He obtained an M.E. in Computer Science from Indian Institute of Science (1987) with highest scores and a B.E. in Electronics from Bangalore University (U.V.C.E.,1983) with a Gold Medal for highest scores. He has published over 250 research papers in the areas of VLSI physical design, VLSI test, parallel processing, electronic design automation and embedded systems in peer-reviewed journals and conferences. He has won four best-paper awards in international conferences of the IEEE and one best paper award in the IETE Journal of Education. He is the author/coauthor/editor of 15 books in the areas of VLSI design and Embedded Systems. He holds 4 US patents in the area of VLSI Test. He is a Fellow of INAE and a senior member of IEEE.
He founded the IEEE CAS Bangalore Chapter and has served as its honorary secretary. He has served as the honorary secretary of VLSI Society of India for 8 years. He established the VLSI Design Test and Symposium (VDAT) in India and was the general chair of this event for 15 years. He has served on the committees of numerous conferences in various capacities such as Program Chair and General Chair. He has served on the editorial committees of several journals, including Journal of Electronic Testing – Theory and Applications (Springer) and Journal of Low Power Electronics (ASP). He has received an award from Zinnov foundation and a recognition from IESA for his work with Indian universities. He received the “Best Blogger” award from TI University Program (2014).
Workshop-2
Workshop Title: "Software-defined Radios: The Workhorse of Modern Telecommunication"
Learning objectives:
Understanding of Software-Defined Radios (SDR), including practical understanding of low-cost SDRs.
Understanding of the SDRs and RF Chain in a Telecommunication System.
Basics of RF-power amplifiers, including field-effect transistors and different technologies (GAS, GaN, CMOS, etc.).
Abstract:
Software-defined radio (SDR) is an inherent part of the modern communication system, where many processes that used to be implemented in hardware are defined in the software domain for flexibility and configurability. This workshop describes various components of SDRs with an understanding of their limitations and the application of ‘software-defined solutions’ to overcome such limitations. Understanding the interplay of analog and digital signal processing for power as well as spectrum-efficient transmission and reception of signals leads to an optimized yet practical radio solution. The SDRs play a crucial role in the (Remote Radio Head) RRH / (Open Radio Unit) ORU development in modern telecommunication systems with the help of the wideband radio frequency (RF) chain. The RF power amplifier is a crucial component for long-distance signal transmission in the RF chain. Therefore, the objective of this workshop is to provide a complete understanding of SDRs and RF chains from a telecommunications point of view.
Brief profile of organizer(s):
Ratnesh Kumar Gaur Principal Engineer, R&D-Wireless Tejas Networks Bengaluru ratneshg@tejasnetworks.com, ratneshgaur@ieee.org (Senior Member IEEE), Ratnesh Kumar Gaur received the B.Tech. degree in electronics and communication engineering from G.B.Pant Engineering College, India, in 2004, and the M.Tech. degrees from the Birla Institute of Technology Pilani in 2020. He received the University Gold Medal during his engineering education. He holds one granted US patent on system architecture design for avionics radio. He has 20 years of professional experience working with systems design and development. He is currently working as Principal Engineer with Tejas Networks Ltd., Bengaluru, India. He has worked with Honeywell, Airbus, Keysight and BEL during his professional carrier.
